In recent years, thanks to the advance of semiconductor technology and circuit technology, the clock speed in LSIs and boards is ever increasing. With such an increase of the clock speed, the interface between LSIs, boards, devices (units), and others is a bottleneck. For transmission and reception of data of digital signals, a need arises also for minimum compensation of delay, and there thus needs to make adjustments to allow transmission of the data in a period of time much shorter than a clock period.
In order to be ready for such an increase of the clock speed, proposed is a technology for automatically correcting any cable delay and any bit-to-bit skew, for example (e.g., refer to Patent Literature 1.).
On the other hand, as to the currently available digital LSIs, a test method thereof has been greatly innovated technologically, and the technology has reached the level of automatically creating a test circuit in charge of a test of chips in the digital LSIs or a test pattern being a signal sequence for the test. In other words, the digital LSIs are those for processing of binary signals with “0” and “1”, and have advantages of being easy to be tested compared with analog LSIs, and being able to simplify a fault model thereof by restrictions to single stuck-at faults, thereby achieving computerization with a method of scan path test or others.
Herein, the scan path test is a method for checking the state of a circuit by using a path (scan path) as a result of establishing a serial connection of flip-flops. Through this scan path, the flip-flops are each stored with any arbitrary value, or any value stored in each of the flip-flops is read through this scan path. In such a scan path test, the flip-flops usually in use are all connected in series in a test mode, and the flip-flops are all so made as to be available for external settings of any arbitrary data (improvement of controllability). Thereafter, the mode is changed to a normal mode, and combinational gates inside of an LSI are each provided with the externally-set data about the flip-flops. An addition of clock is then made so that the output of such gates is captured into any same flip-flop. Lastly, the mode is then changed to the test mode again for scan-out (improvement of observability), and a signal of the internal gate is output to the outside of the LSI, thereby making a determination whether the gate output is normal or abnormal. This operation is repeated until any desired fault coverage is achieved. Such an example of utilizing the scan path test for a text of digital LSIs has been widely known (e.g., refer to Patent Literature 2.).
Citation List
Patent Literature
Patent Literature 1: Japanese Unexamined Patent Publication No. 11-112483 (FIG. 1)
Patent Literature 2: U.S. Pat. No. 2,550,521 (FIG. 5)